Many portable products, such as cell phones, laptop computers, personal data assistants (PDAs) or the like, utilize a processor executing programs, such as, communication and multimedia programs. The processing system for such products includes a processor complex for processing instructions and data. The functional complexity of such portable products, other personal computers, and the like, requires high performance processors and memory. At the same time, portable products have a limited energy source in the form of batteries and are often required to provide high performance levels at reduced power levels to increase battery life. Many personal computers are also being developed to provide high performance at low power drain to reduce overall energy consumption.
Internal to a processor complex, signal paths and pipeline stages are designed to meet a worst case critical timing path corresponding to a desired clock frequency. Memory elements, logic gates, flip-flops, and wires interconnecting the elements introduce delays in the critical path timing limiting the number of functional elements in a pipeline stage dependent upon the clock frequency. As a consequence, many processors use a large number of pipeline stages to execute instructions of varying complexity and achieve gigahertz (GHz) clock frequencies required to meet a product's functional requirements. Since power is a function of frequency, switching capacitance, and the square of the supply voltage, reducing power requires the reduction of at least one of these three variables. Since gigahertz frequency operation is many times required by a product's functions, reducing frequency is limited to less demanding functions. Switching capacitance is a function of an implementation and the technology process used to manufacture a device and once a design is instantiated in silicon this variable cannot be changed. One consequence of reducing the supply voltage is that as the supply voltage is reduced the logic and memory elements slow down, increasing the difficulty in meeting frequency requirements.
In order to meet a worst case critical timing path in a processor complex, the worst case critical timing paths for all the signal paths within the processor complex are analyzed and the longest path among these becomes the critical timing path that governs the processor complex's highest possible clock frequency. To guarantee that this clock frequency is met, the supply voltage is specified to be greater than or equal to a worst case minimum voltage. For example, it may be determined that when executing a floating point instruction, a signal path through a floating point multiplier may be the longest critical timing path in the processor complex. The power supply voltage is determined such that the worst case timing path through the floating point multiplier meets the desired clock frequency.
Since any instruction may be selected from a processor's instruction set for execution at any time, the processor complex generally operates in preparation for the worst case timing path. As a consequence, power is wasted when executing instructions having a critical timing path less than the worst case timing path. Unfortunately, the supply voltage cannot be easily changed to match the instruction-by-instruction usage of gigahertz processors. Variable voltage regulators require microseconds or milliseconds to adjust a supply voltage.